1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a digital Phase Locked Loop (PLL) circuit, which can be applied for digital signal processing apparatuses or systems such as a computer and a data transmission or exchange system.
2. Description of the Prior Art
A conventional digital signal processing system is shown in FIG. 1, which contains first and second mounting boards 7 and 8 and a clock signal generator 6 deposited outside the boards 7 and 8.
The first mounting board 7 has a clock signal distribution buffer 71 and two semiconductor Large Scale Integrated (LSI) circuit chips 72 and 73 for digital signal processing such as a gate array. A clock signal generated in the clock signal generator 6 is supplied to the distribution buffer 71 and is distributed to the LSI circuit chips 72 and 73, respectively.
Similarly, the second mounting board 8 has a clock signal distribution buffer 81 and two semiconductor LSI circuit chips 82 and 83 for digital signal processing. The clock signal supplied to the distribution buffer 81 is distributed to the LSI circuit chips 82 and 83, respectively.
The chip 72 receives a data signal from an LSI circuit chip (not shown) and transfers a data signal produced therein to the chip 73 mounted on the same board 7. The chip 73 transfers a data signal produced therein to the chip 82 mounted on the second mounting board 8.
The chip 82 receives the data signal transferred from the LSI circuit chip 73 and transfers a data signal produced therein to the chip 83. The chip 83 transfers a data signal produced therein to an LSI circuit chip (not shown).
The data signal transfers between the adjacent two chips are synchronized with the clock signal.
There is a problem with the conventional digital signal processing system shown in FIG. 1 in that the data signal transfers cannot be carried out correctly because of clock skew due to variation in wiring length and/or circuit load in the LSI chips 72, 73, 82 and 83 generated during their fabrication process sequence.
In particular, the problem becomes important in the case of the data transfer between the two LSI chips mounted on the different boards. In the system of FIG. 1, the clock signal is supplied to the LSI chip 73 through the clock signal distribution buffer 71 and is supplied to the LSI chip 82 through the clock signal distribution buffer 81, so that arises a time lag between the moments at which the LSI chips 73 and 82 receives the clock signals.
Generally, due to dispersion in electrical characteristics, an LSI chip fluctuates in delay time from the input of a clock signal to the output of its data signal and fluctuates in set up hold time from the input of a data signal. As a result, the data signal transfers between the adjacent two ones of the LSI chips 72, 73, 82 and 83 tends to be carried out incorrectly.
Further, there is another problem in that the above data signal transfers are difficult to carry out when the clock signal is high in frequency.